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Why does a higher post-synaptic cell resistance lead to a higher voltage change when current is applied?

Why does a higher post-synaptic cell resistance lead to a higher voltage change when current is applied?


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In the "Principles of Neural Science" 5th edition in the discussion about electrical synapses it says:

During excitatory synaptic transmission at an electrical synapse, voltage-gated ion channels in the presynaptic cell generate the current that depolarizes the postsynaptic cell. Thus these channels not only depolarize the presynaptic cell above the threshold for an action potential but also generate sufficient ionic current to produce a change in potential in the postsynaptic cell.

To generate such a large current, the presynaptic terminal must be big enough for its membrane to contain many ion channels. At the same time, the postsynaptic cell must be relatively small. This is because a small cell has a higher input resistance (Rin) than a large cell and, according to Ohm's law (V = I x Rin), undergoes a greater voltage change in response to a given presynaptic current (I).

I get that Ohm's law states this, but what is really going on? Why should the resistance encountered by charge as it is moving through gap-junctions from the presynaptic to the postsynaptic cell affect the voltage (electrical potential) across the membrane of the postsynaptic cell with its environment. Once the charge gets to the postsynaptic cell, it seems like it should no longer be affected by the resistance it encountered along the way.


If you consider the electrical synapse a simple series RC circuit, with the resistance in the synapse and the capacitor as the postsynaptic cell, then you are correct that the value of R only changes the charge time for the capacitor (from a DC source, but not it's final voltage (at t = infinity).

($ au = RC$)

On the other hand, this model is too simplistic for the electrical synapse because you also have losses (discharge) to the outside of the cells. Image from the book:

And a more realistic circuit is created with extra (parallel) resistors below for the extracellular discharge. Note what happens when the 2nd resistor (discharge of postsynaptic cell to inter-cellular space) is introduced in the circuit (switch closed): the voltage charge on capacitor drops significantly.

You basically have to "beat" or minimize this voltage drop, and one way to do this is to have a lower series resistor (another is of course a higher isolation [i.e. resistor] from the intercellular space). When the synapse resistance is 10 times lower than in the previous circuit, the voltage drop on the synapse is much lower, and so the voltage on the capacitor is higher, even with the switch closed:

You can play with the circuit here; it's set for the first set of resistor values; you need to right-click on a resistor and pick "edit" to change it's value; I could have added another switch and resistor to achieve that change for the synapse… but I didn't want to complicate the circuit conceptually.


Voltage determines the kind of chemistry at each electrode. Gold is purified by plating the anode to the cathode at minimum voltage for the half-reaction, so impurities either do not dissolve and do not plate out. Copper electrorefining electrode mud contains valuable trace elements in concentrated from.

Current determines the amount of chemistry,

96,500 coulombs/mole of electrons.

Cell internal resistance converts input energy, power multipleid by time, $ce$, into useless heat. You then want small electrode spacing and good electrolyte stirring. You then need enough voltage to do the chemistry, plus more to compensate for resistance losses, but not so much voltage that undesirable chemistries are enabled. Does cell resistance increase (ohmic) or decrease with temperature?

Regarding your question: "Is the resistance fixed, or can I do anything to lower it?"

The energy used in electrolysis produces both product and waste heat. Naturally, you want to maintain sufficient production while limiting wasted energy.

A few important formulas:

Things that effect resistance, and their effects on product versus waste heat and rate of production: Adjusting each parameter individually:

Voltage: Per unit of energy supplied, in general, a lower voltage produces more product and less waste heat from electrolysis. Below a certain threshold voltage no electrolysis will occur. Although less power is consumed to produce the same product at a low voltage at a higher efficiency, the process proceeds slower because with a lower voltage, there is less current and power is consumed more slowly. Alternativly one can increase the voltage to drive more current and produce their product faster, but this happens at an expence to efficency.

Electrolyte type and concentration: Different electrolytes have different capacities to conduct and Its concentration above or below an ideal will negatively effect the electrolyte's capactiy to conduct electricity.

Temperature: Increasing the temperature of electrolyte lowers the resistance of an electrolyte. Additionally, some of the energy used to break up water's molecular bonds is provided by the thermal energy of molecules bouncing off each other. But, the effect really only becomes appreciable with high temperature electrolysis, like say 800c.

Surface Area: Surface area and current are proportional. All other parameters being equale, if you double the surface area of your electrodes, you effectivly half the resistance and double the current.

Spacing: Decreasing the spacing between electrodes decreases resistance.


Why does a higher post-synaptic cell resistance lead to a higher voltage change when current is applied? - Psychology

Neural control initiates the formation of actin – myosin cross-bridges, leading to the sarcomere shortening involved in muscle contraction. These contractions extend from the muscle fiber through connective tissue to pull on bones, causing skeletal movement. The pull exerted by a muscle is called tension. The amount of force created by this tension can vary, which enables the same muscles to move very light objects and very heavy objects. In individual muscle fibers, the amount of tension produced depends primarily on the amount of cross-bridges formed, which is influenced by the cross-sectional area of the muscle fiber and the frequency of neural stimulation.

Muscle tension: Muscle tension is produced when the maximum amount of cross-bridges are formed, either within a muscle with a large diameter or when the maximum number of muscle fibers are stimulated. Muscle tone is residual muscle tension that resists passive stretching during the resting phase.

Cross-bridges and Tension

The number of cross-bridges formed between actin and myosin determine the amount of tension that a muscle fiber can produce. Cross-bridges can only form where thick and thin filaments overlap, allowing myosin to bind to actin. If more cross-bridges are formed, more myosin will pull on actin and more tension will be produced.

Maximal tension occurs when thick and thin filaments overlap to the greatest degree within a sarcomere. If a sarcomere at rest is stretched past an ideal resting length, thick and thin filaments do not overlap to the greatest degree so fewer cross-bridges can form. This results in fewer myosin heads pulling on actin and less muscle tension. As a sarcomere shortens, the zone of overlap reduces as the thin filaments reach the H zone, which is composed of myosin tails. Because myosin heads form cross-bridges, actin will not bind to myosin in this zone, reducing the tension produced by the myofiber. If the sarcomere is shortened even more, thin filaments begin to overlap with each other, reducing cross-bridge formation even further, and producing even less tension. Conversely, if the sarcomere is stretched to the point at which thick and thin filaments do not overlap at all, no cross-bridges are formed and no tension is produced. This amount of stretching does not usually occur because accessory proteins, internal sensory nerves, and connective tissue oppose extreme stretching.

The primary variable determining force production is the number of myofibers (long muscle cells) within the muscle that receive an action potential from the neuron that controls that fiber. When using the biceps to pick up a pencil, for example, the motor cortex of the brain only signals a few neurons of the biceps so only a few myofibers respond. In vertebrates, each myofiber responds fully if stimulated. On the other hand, when picking up a piano, the motor cortex signals all of the neurons in the biceps so that every myofiber participates. This is close to the maximum force the muscle can produce. As mentioned above, increasing the frequency of action potentials (the number of signals per second) can increase the force a bit more because the tropomyosin is flooded with calcium.


EXPERIMENT DESIGN SETUP WITH CLEAR LABELS

  1. Put on safety goggles, lab coats, gloves and masks for safety.
  2. Handle all materials carefully.
  3. Have a clear and clear working space for the experiment.
  4. Do not consume any of the materials used, and keep them away from the eyes.
  5. Complete all trials in the same area/room, at the same time of the day, using the same materials.
  6. Clean up the lab area after the experiment.
  7. Wash all materials thoroughly with warm water and soap after the experiment.

Laboratory Methods

Laboratory Methods Highlights

· This week, instead of stimulating a nerve with a reflex hammer via stretch receptors, we will stimulate a nerve directly with stimulating electrodes.

· Please wear short sleeves or sleeves that can be rolled above the elbow, half way up the brachium.

· A stimulating electrode delivers a mild electric shock, which, if sufficiently strong, depolarizes the membranes of neurons, causing them to fire.

· Neurons stimulated with stimulating electrodes behave like other neurons, except that when stimulating the fibers of a nerve, we may provoke action potentials in both sensory and motor fibers at the same time.

· In this lab we will stimulate the ulnar nerve and determine the outcome of increasing stimulus strength (in mAmps).

· Later, we will re-stimulate the ulnar nerve from two different locations along the arm in order to determine the conduction velocity.

Equipment Required: IXTA data acquisition unit, iWire-B3G cable and three EMG lead wires, disposable snap electrodes, HV stimulator lead wires.

I. Equipment Setup: Start the Software

Turn on the iWorx hardware box at the switch on the back, and select the Week7_NerveConduction.iwxset file from the P-drive.

II. Equipment Setup: Electrode Placement

  1. The subject should remove all jewelry from his/her left or right hand and wrist.
  2. Study the pathway of the ulnar nerve in the picture (below).

3. Clean the areas where the electrodes will be attached with an alcohol pad. Lightly abrade the skin in those areas.

  1. Obtain Seven disposable electrodes. Label 5 them on the pointed tab with the letters A through E.
  2. Cut down the electrodes so just the Medline logo shows. Keep the plastic backing on them to reduce adhesive build up on the scissors.
  • Place A on the medial edge of the little finger of the right hand, so the electrode button/snap is just above the first knuckle. This is for the RED (+) recording electrode in Figure HN-3-S2.
  • Place B on the medial edge of the palm, so the electrode button/snap is at the base of the little finger. This is for the BLACK (-) recording electrode on the hand.
  • Place C so the electrode button/snap is on the medialedge of the wrist just above the crease of the wrist. This is for the GREEN ground electrode on the hand.
  • Warning: Before connecting the IXTA stimulating electrodes to the subject, check the Stimulator Control Panel in the LabScribe toolbar to make sure the amplitude value is set to zero (0 AMP).

Next, attach the remaining 2 electrodes to the subject&rsquos arm so that they are placed on the pathway of the Ulnar Nerve in the following configuration:

  • Place D the medial edge of the forearm, so the electrode button/snap is above the wrist crease. Attach the BLACK (-) stimulating electrode.
  • Place E, the positive stimulating electrode, right above the negative stimulating electrode towards the medial side of the forearm. Attach the RED(+) stimulating electrode.
  • Electrodes F and G (in the photo) will be placed later for Exercise 2.
  • Videos of proper electrode placement for Exercises 1 and 2 are found on the P-Drive.

Safety precautions for this lab:

You will deliver mild electric shocks to either yourself or a volunteer experimental subject. The equipment you use to do this is carefully designed to keep the parameters of the electroshocks well within a safe range, and this experiment is safe and fun. Nevertheless, we ask that you place stimulating electrodes on the arms only, and only place electrodes on the same side of the body (never on both arms at the same time).

If you think you may be pregnant or if you suffer from known heart conditions or have an artificial heart pacemaker please do not volunteer as an experimental subject this week.


3 Answers 3

The answer depends on the circumstances: how do you change the resistance? Both the drift velocity and the number of available charge carriers can be changed.

In a basic Drude model for electrical transport both, $n$, the charge carrier density and $ au$, the time between collisions determine the resistance:

$mathbf = left( frac ight) mathbf.$ Here, $mathbf$ is the current density and $mathbf$ the applied electrical field. The term in parentheses characterizes the material properties, i.e. its resistance.

By changing to a different material you can influence both, $n$ and $ au$, so both cases are possible.

Your understanding is correct. From $V=IR$ if voltage stays the same while resistance is increased, the current should be decreased.

But if you have heard of another equation $I = frac$

If current(I) is increased and the charge $Q$ is fixed (Charge is fixed if the power supply is from power cells like battery). Time will be decreased.

Which means that

The charges are moving faster! Because numbers of charge are fixed by the size of battery.

Imagine a four lanes road. Then in 300 meters ahead, there is a construction for road maintenance for three lanes. Making only one lane available to pass. Cars from 4 lanes must combine into one lane, making traffic jams and cause everyone to get home slower.

4 lanes road = Normal wire

1 lane road and traffic jams = Problems cause by resistance.

Home= + terminal of battery

Like some phone battery have 10000mAh. Which actually is the value of $Q$ but in milliamperes * hours not ampere * seconds. So 1 mAh is equal to 5/18 Coulomb.


Memristor-Based Neural Networks

Neuron Biological Mechanisms and Memristive Synapse

The human brain can solve complex tasks, such as image recognition and data classification, more efficiently than traditional computers. The reason why a brain excels in complicated functions is the large number of neurons and synapses that process information in parallel. As shown in Figure 3, when an electrical signal is transmitted between two neurons via axon and synapse, the joint strength or weight is adjusted by the synapse. There are approximately 100 billion neurons in an entire human brain, each with about 10,000 synapses. Pre-synaptic and post-synaptic neurons transfer and receive the signal of excitatory and inhibitory post-synaptic potentials by updating synaptic weights. Long-term potentiation (LTP) and long-term depression (LTD) are important mechanisms in a biological nervous system, which indicates a deep-rooted transformation in the connection strengths between neurons. According to the interval between pre-synaptic and post-synaptic action potentials or spikes, the phenomenon of synaptic weight modification is known as spike-timing-dependent plasticity (STDP) (Yan et al., 2018a, 2019c). Due to scalability, low power operation, non-volatile features, and small on-chip area, memristors are good candidates for artificial synaptic devices to mimicking the LTP, LTD, and STDP behaviors (Jo et al., 2010 Ohno et al., 2011 Kim et al., 2015 Wang et al., 2017 Yan et al., 2017).

Figure 3. Schematic of two interconnected neurons by synapses.

There are some key requirements for memristive devices in neural network applications. For example, a wide range of resistance is required to enable sufficient resistance states devices are required to have low resistance fluctuations and low device-to-device variability a higher absolute resistance is required for low power dissipation and high durability is required for reprogramming and training (Choi et al., 2018 Yan et al., 2018b, 2019a Xia and Yang, 2019). A concern with device stability is resistance drift, which occurs over time or with the environment. Resistance drift causes undesirable changes in synapse weight and blurs different resistance states, ultimately affecting the accuracy of neural network computation (Xia and Yang, 2019). To deal with this drift challenge, improvements can be made in three aspects: (1) material device engineering, (2) circuit design, and (3) system design (Alibart et al., 2012 Choi et al., 2018 Jiang et al., 2018 Lastras-Montaño and Cheng, 2018 Yan et al., 2018b, 2019a Zhao et al., 2020). For example, as for the domain of material engineering, threading dislocations can be used to control programming variation and enhance switching uniformity (Choi et al., 2018). In terms of circuit-level design, a module of two series memristors and a transistor with the smallest size can be used, thus, the resistance ratio of the memristor can be encoded to compensate for the resistance drift (Lastras-Montaño and Cheng, 2018). For the system-design level, device deviation can be reduced by protocols, such as closed loop peripheral circuit with a write-verify function (Alibart et al., 2012). In order to obtain linear and symmetric weight update in LTP and LTD for efficient neural network training, optimized programming pulses can be used to excite memristors with either fixed-amplitude or fixed-width voltage pulses (Jiang et al., 2018 Zhao et al., 2020). Note it is inevitable to increase energy consumption if the memristor resistance value is changed through complex programmable pulses.

The comparison of different memristive synapse circuit structures is shown in Table 2 (Kim et al., 2011a Wang et al., 2014 Prezioso et al., 2015 Hong et al., 2019 Krestinskaya et al., 2019). Single memristor synapse (1M) crossbar arrays in neural networks have the lowest complexity and low power dissipation. However, it suffers from sneak path problems and complex peripheral switch circuits. Synapses with two memristors (2M) have a more flexible weight range and better symmetric LTP and LTD, but the corresponding chip area will be doubled. A synapse with one memristor and one transistor (1M-1T) has the advantage of solving the sneak path problem, but it also occupies a large area in the large-scale integration of neural networks. A bridge synapse architecture with four memristors (4M) provides a bidirectional programming mechanism with a voltage input voltage output. Due to the significant on-chip area overhead, the 1M-1T and 4M synapses may not be applicable for large-scale neural networks.

Table 2. Comparison of different structure memristive synapse circuit.

Memristor-Based ANNs

The basic operations of classical hardware ANNs include multiplication, addition, and activation, which are accomplished by CMOS circuits such as GPUs. The weights are typically saved in SRAM or DRAM. Despite the scalability of CMOS circuits, they are still not enough for ANN applications. Furthermore, the SRAM cell size are too big to be integrated at high density. DRAM needs to be refreshed periodically to prevent data decay. Whether it is SRAM or DRAM, it often needs to interact with CMOS cores. No matter SRAM or DRAM, the data needs to be fetched by to the cache and register files of the digital processors before processing and returned through the same databus, leading to significant speed limit and large energy consumption, which is the main challenge for deep learning and big data applications (Xia and Yang, 2019). Nowadays, ANNs feature for large number of computational parameters stored in memory compared to classical computation. For example, a two-layer 784-800-10 fully-connected deep neural network in the MNIST dataset has 635,200 interconnections. A state of the art keep neural network like Visual Geometry Group (VGG) has a few millions of parameters. These factors pose a huge challenge to the implementation of ANN hardware. The memristor's non-volatility, lower power consumption, lower parasitic capacitance, and reconfigureable resistance states, high speed, and adaptability lead to a key role in ANN applications (Xia and Yang, 2019). An ANN is an information processing model which are derived from mathematical optimization. A typical ANN architecture and its memristor crossbar are shown in Figure 4. The system usually consists of three layers: an input layer, a middle layer or a hidden layer, and an output layer. The connected units or nodes are neurons which are usually series by weighted-sum module and activation function module. Neurons also perform tasks of decoding, control, and signal routing. Due to its powerful signal processing capability, CMOS analog and digital logic circuits are the best candidates for neurons hardware implementation. In Figure 4, arrow or connecting lines represent synapses, and their weights represent the connection strengths between two neurons. Assume the weight modulation matrix Wij in a memristor synapse crossbar is a M × N dimensinal matrix, where i(i = 1, 2, …, N) and j(i = 1, 2, …, M) are the index numbers of the output and input ports of the memristor crossbar. Wij between pre-neuron input vector Xj and post-neuron output vector Yi is a matrix-vector multiplication operation, expressed as Equation (1) (Jeong and Shi, 2018).

The matrix W can be continuously adjusted until the difference between the output value y and the target value y * is minimized. The Equation (2) shows the synaptic weight tunning process with the gradient of output error (y–y * ) 2 under a training rate (Huang et al., 2018). Therefore, a memristor crossbar is equal to a CMOS adder plus a CMOS multiplier and an SRAM (Jeong and Shi, 2018), because data are computed, stored, and regenerated on the same local device (i.e., a memristor itself). Besides, a crossbar can be vertically integrated into three dimensions (Seok et al., 2014 Lin et al., 2020 Luo et al., 2020). In this way, it saves much chip area and power consumption. Due to the memristor synapse update and save weight data on itself, the memory wall problem with von Neumann bottleneck is solved.

Figure 4. Typical ANN architecture and its memristor crossbar.

Researchers have developed various topologies and learning algorithms for software-based or hardware-based ANNs. Table 3 provides a comparison of typical memristive ANNs, including single-layer perceptron (SLP) or multi-layer perceptron (MLP), CNN, cellular neural network (CeNN), and recurrent neural network (RNN). SLP and MLP are classic neural networks with well-known learning rules such as Hebbian learning, backpropagation. Although a lot of ANN studies have been verified by simulations or small-scale implementation, a single-layer neural network with 128 × 64 1M-1T Ta/HfO2 memristor array has been experimentally demonstrated with an image recognition accuracy of 89.9% for the MNIST dataset (Hu et al., 2018). CNNs (referred to as space-invariant or shift-invariant ANNs) are regularized versions of MLP. Their hidden layers usually contain multiple complex activation functions, and perform convolution or regional maximum value operations. Researchers have demonstrated an over 70% of accuracy in human behavior video recognition with a memristor-based 3D CNN (Liu et al., 2020). It should be emphasized that this verification is only a software simulation result, while the on-chip hardware demonstration is still very challenging, especially for deep CNNs (Wang et al., 2019a Luo et al., 2020 Yao et al., 2020). CeNN is a massively parallel computing neural network, whose communication features are limited to between adjacent cell neurons. The cells are dissipative non-linear continuous-time or discrete-time processing units. Due to their dynamic processing capability and flexibility, CeNNs are promising candidates for real-time high frame rate processing or multi-target motion detection. For example, a CeNN with 4M memristive bridge circuit synapse has been proposed for image processing (Duan et al., 2014). Unlike classic feed forward ANNs, RNNs have a feedback connection that enables temporal dynamic behavior. Therefore, it is suitable for speech recognition applications. Long short-term memory (LSTM) is a kind of useful RNN structure for deep learning. Hardware implementation of LSTM networks based on memristors have been reported (Smagulova et al., 2018 Li et al., 2019 Tsai et al., 2019 Wang et al., 2019a).

Table 3. Typical architectures of Memristive ANNs.

Due to atomic-level random defects and variability in the conductance modulation process, non-ideal memristor characteristics are the main causes of learning accuracy loss in ANNs. This phenomenon is manifested in the following aspects of memristor: asymmetric non-linear weight change between potentiation and depression, limited ON/OFF weight ratio and device variation. Table 4 shows the main strategies for how to deal with these issues. One can mitigate the effects of non-ideal memristor characteristics on ANN accuracy from four levels: device materials, circuits, architectures, and algorithms. At device materials level, switching uniformity and analog on/off ratio can be enhanced by optimizing redox reaction at the metal/oxide interface, adopting threading dislocations technology or heating element (Jeong et al., 2015 Lee et al., 2015 Tanikawa et al., 2018). At circuits level, one can use customized excitation pulse or hybrid CMOS-memristor synapses to mitigate memristor non-ideal effects (Park et al., 2013 Li et al., 2016 Chang et al., 2017 Li S. J. et al., 2018 Woo and Yu, 2018). At architectures level, common techniques are multiple memristors cell for high redundancy, pseudo-crossbar array, and peripheral circuit compensation (Chen et al., 2015). Co-optimization between memristors and ANN algorithms is also reported (Li et al., 2016). However, it should be noted that implementation of these strategies inevitably brings side effects, such as high manufacturing cost, large power consumption, large chip area, complex peripheral circuits, or inefficient algorithm. For example, the non-identical pulse excitation or bipolar-pulse-training methods improve the linearity and symmetry of memristor synapses, but it increases the complexity of peripheral circuits, system power consumption, and chip area. Therefore, trade-offs and co-optimization need to be made at each design level to improve the learning accuracy of ANNs (Gi et al., 2018 Fu et al., 2019). Figure 5 is a collaborative design example from bottom-level memristor devices to top-level training algorithms (Fu et al., 2019). The conductance response (CR) curve of memristors is first measured to obtain its non-linearity factor. Then, the CR curve is divided into piecewise linear segments to obtain their slope, and the pulse width of the excitation pulse is inversely proportional to the slope. These data are stored in memory for comparison and correction by memristor crossbars during the update. Through this method, the ANN recognition accuracy is finally improved.

Table 4. ANNs learning accuracy improvement by mitigating memristor non-ideal effects.

Figure 5. Co-design from memristor non-ideal characteristics to the ANN algorithm (Fu et al., 2019).

The memristor-based ANN applications can be software, hardware or hybrid (Kozhevnikov and Krasilich, 2016). Software networks tend to be more accurate than their hardware counterparts because they do not have the analog element non-uniformity issues. However, hardware networks feature better speed and less power consumption due to non-von Neumann architectures (Kozhevnikov and Krasilich, 2016). In Figure 6, a deep neuromorphic accelerator ANN chip with 2.4 million Al2O3/TiO2-xmemristors was designed and fabricated (Kataeva et al., 2019). This memristor chip consists of a 24 × 43 array with a 48 × 48 memristor crossbar at each intersection, which means its complexity is about 1,000 times higher than previous designs in the literature. This work is a good starting point for the operation of medium-scale memristor ANNs. Similar accelerators have appeared in the last 2 years (Cai et al., 2019 Chen W.-H. et al., 2019 Xue et al., 2020).

Figure 6. A deep neuromorphic ANN chip with 2.4 million memristor devices (Kataeva et al., 2019).

Memristive neural networks can be used to understand human emotion and simulate human operational abilities (Bishop, 1995). The well-known PavlTov associative memory experiment has been implemented in memristive ANNs with a novel weighted-input-feedback learning method (Ma et al., 2018). As more input signals, neurons, and memristor synapses, complex emotional processing will be achieved in further AI chips. Due to the material challenge and the lack of effective models, most of the demonstrations are limited to small-scale simulations for simple tasks. The shortcomings of memristors are mainly the non-linearity, asymmetry, and variability, which seriously affect the accuracy of ANNs. Moreover, the peripheral circuits and interface must provide superior energy efficiency and data throughput.

Memristor-Based SNN

Inspired by cognitive and computational methods of animal brains, the third-generation neural network, SNN, makes desirable properties of compact biological neurons mimic and remarkable cognitive performance. The most prominent feature of SNN is that it incorporates the concept of time into operations with discrete values, while the input and output values of the second-generation ANNs are continuous. SNN can better leverage the strength of biological paradigm of information processing, thanks to the hardware emulation of synapses and neurons. ANN is calculated layer by layer, which is relatively simple. However, spike trains in SNN are relatively difficult to understand and efficient coding methods for these spike trains are not easy. These dynamic events driven spikes in SNN enhance the ability to process spatio-temporal or real-world sensory data, with fast adaptation and exponential memorization. The combination of spatio-temporal data allows SNN to process signals naturally and efficiently.

Neuron models, learning rules, and external stimulus coding are key research areas of SNN. The Hodgkin & Huxley (HH) model, leaky Integrate-and-Fire (LIF) model, spike response model (SRM), and Izhikevich model are the most common models of neurons (Hodgkin and Huxley, 1952 Chua, 2013 Ahmed et al., 2014 Pfeiffer and Pfeil, 2018 Wang and Yan, 2019 Zhao et al., 2019 Ojiugwo et al., 2020). The HH model is a continuous-time mathematical model based on conductance. Although this model is based on the study of squid, it is widely used in lower or higher organisms (even humans being). However, since complex non-linear differential equations are set with four variables, this model is difficult to achieve high accuracy. Chua established the memristor model of Hodgkin-Huxley neurons and proved that memristors can be applied to the imitation of complex neurobiology (Chua, 2013). The Izhikevich model integrates the bio-plasticity of HH model with simplicity and higher computational efficiency. The HH and Izhikevich models are calculated by differential equations, while the LIF and SRM models are computed by an integral method. SRM is an extended version of LIF, and the Izhikevich model can be considered as a simplified version of the Hodgkin-Huxley model. These mathematical models are the results of different degrees of customization, trade-offs and biological neural network optimization. Table 5 shows a comparison of several memristor-based SNNs. It can be seen that these SNN studies are based on STDP learning rules and LIF neurons. Most of them are still in simple pattern recognition applications, only a few of which have hardware implementations.

Table 5. Comparison of several memristor-based SNNs.

The salient features of SNNs are as follows. First, biological neuron models (e.g., HH, LIF) are closer to biological neurons than neurons of ANN. Second, the transmitted information is time or frequency encoded discrete-time spikes, which can contain more information than traditional networks. Third, each neuron can work alone and enter a low power standby mode when there is no input signal. Since SNNs have been proven to be more powerful than ANNs in theory, it is natural to widely use SNNs. Since the spike training cannot be differentiated, the gradient descent method cannot be used to train SNNs without losing accurate temporal information. Another problem is that it takes a lot of computation to simulate SNNs on normal hardware, because it requires analog differential equations (Ojiugwo et al., 2020). Due to the complexity of SNNs, efficient learning rules that meet the characteristics of biological neural networks have not been discovered. This rule is required to model not only synaptic connectivity but also its growth and attenuation. Another challenge is the discontinuous nature of spike sequence, which makes many classic ANN learning rules unsuitable for SNNs, or can only be approximated, because the convergence problem is very serious. Meanwhile, many SNNs studies are limited to theoretical analysis and simulation of simple tasks rather than complex and intelligent tasks (e.g., multiple regression analysis, deductive and inductive reasoning, and their chip implementation) (Wang and Yan, 2019). Although the future of SNNs is still unclear, many researchers believe that SNNs will replace deep ANNs. The reason is that AI is essentially a biological brain mimicking process, and SNNs can provide a perfect mechanism for unsupervised learning.

As shown in Figure 7, a neural network is implemented with CMOS neurons, CMOS control circuits, and memristor synapses (Sun, 2015). The aggregation module, leaky integrate and fire module are equivalent to the role of dendrites and axon hillocks, respectively. Input neurons signals are temporally and spatially summed through a common-drain aggregation amplifier circuit. A memristor synapse gives the action potential signal a weight and its output signal, that is, a post-synaptic potential signal is transmitted to post-neurons. Using the action potential signal and feedback signals from post-neurons, the control circuit and synaptic update phase provide potentiation or depression signals to memristor synapses. According to the STDP learning rules, the transistor-level weight adjustment circuit is composed of a memristor device and CMOS transmission gates. The transmission gates are controlled by potentiation or depression signals. The system is very similar to the main features of biological neurons, which is useful for neuromorphic SNN hardware implementation. A more complete description of SNN circuits and system applications is shown in Figure 8 (Wu and Saxena, 2018). The system consists of event-driven CMOS neurons, a competitive neural coding algorithm [i.e., winner take all (WTA) learning rule], and multi-bit memristor synapse array. A stochastic non-linear STDP learning rule with an exponential shaped window learning function is adopted to update memristor synapse weights in situ. The amplitude and additional temporal delay of the half rectangular half-triangular spike waveform can be adjusted for dendritic-inspired processing. This work demonstrates the feasibility and excellence of emerging memristor devices in neuromorphic applications, with low power consumption and compact on-chip area.

Figure 7. CMOS neuron and memristor synapse weight update circuit (Sun, 2015).


The battery capacity specification (eg X mAh) tells you that your battery can run for 1 hour providing X milliamps until it is depleted. This doesn't always scale with time, for example you probably won't run for 1/2 hour if you draw 2*X milliamps, but this is another discussion.

To answer your question, a greater mAh will allow you to use your battery for longer before it depletes, in terms of current draw.

However, for the same battery model, the C-rating ($C$)(the maximum current you can safely, constantly draw from the battery) stays constant. Thus, since it is defined as $I_ = C cdot X$, higher C-ratings will also allow you to draw higher instantaneous currents, hence more power.

Neither, it means more energy and it implies more power.

Think of energy as the thing you "spend" to do work, and power is how much work you get done in a particular period of time.

Typically a battery is rated for power with something called a "C" rating, or how much power it would take to drain the battery in one hour.

Since output power of a battery is voltage times current, the C rating can be calculated as nominal voltage times the amp-hour rating, divided by the nominal voltage times an hour.

The nominal voltage cancels itself, and you're just left with the "amp" portion of the battery's amp-hour rating.

This means a 5000mAh battery has a 1C rating of 5000mA, but the output power of the battery is that times nominal voltage, so a 5000mAh battery pack rated for 1C would have less power available than a 2500mAh pack rated for 10C because the 5Ah pack's available output power is limited to (voltage) times 5A where the 2.5Ah pack's available output power is limited to (voltage) times 25A. The smaller pack, with the higher C rating, is capable of delivering 5 times the power in this example.

Regarding run times, that depends on the C rating for the battery. The higher it is, the more power you are (safely) able to draw at once, which means that you can get more power from a high C battery but, because power is how quickly you're spending energy, that means you'll drain the battery faster.

Ultimately, though, assuming the batteries have the same C rating, the larger capacity battery will have more power available because the C rating is driven by battery capacity.

Given the same applied load (meaning you don't actually use all that available power), the battery with the larger capacity will last longer because you are now drawing power at a lower C value.

I understand C values can be confusing, so if you want some examples just let me know!

I have mentioned several times now the phrase "available power" because of what I worry is a misconception about batteries and electricity in general. Just because a battery can deliver 25A doesn't mean the battery will deliver 25A. The cold cranking amperage rating (CCA) on your car battery is in the hundreds of amps, but if all you're doing is listening to the radio with your car off, you're drawing a negligible amount of power.

This is all because of Ohm's Law, which says that the current through a device is equal to the applied voltage, relative to the resistance in that device. That is, $I = frac$ (more commonly expressed as $V=IR$).

This means that if you don't change the electrical load - you keep the same motors running at the same speed - then the effective resistance of the load doesn't change. This in turn means that, if you don't change the terminal voltage of the battery, the current supplied to the load doesn't change.

If the voltage is constant, and the current is constant, then the applied power is constant, even if the available power changes. When your phone is in your hand, the battery inside the phone is powering it. When you plug your phone in, you might be connecting it electrically to a turbine the size of a strip mall. The change in available power doesn't mean you automatically consume all of the available power.

By this, I mean that, as long as your current battery is capable of supplying the load (your voltage bus doesn't brown out), then switching to a larger capacity battery will not improve your performance at all, even though it may have more available power. Electrical devices "take what they need" and nothing more.


Transduction of noxious mechanical stimuli

Whereas heat- and chemical-induced nociceptor responses correlate with pain perception in humans (9, 24), mechanical stimulation of C-MH (24) and rapidly adapting A-HTM (18) fibers may not (24) (Tables ​ (Tables1 1 and ​ and2). 2 ). The perception of pinprick pain intensity, however, is related to activity in capsaicin-insensitive A-fiber nociceptors (e.g., A-M and A-MH type I) (78). Transduction channels mediating mammalian noxious (and innocuous) mechanical stimuli have been elusive (5, 91, 92). Transduction in soma membranes on a submillisecond time scale suggests direct gating by pressure of ion channels with NSC and possibly Na + permeability (91). No orthologs for the well-studied prokaryotic mechanosensitive channels MscL and MscS are present in mammalian genomes (93). In addition, there is no strong evidence that mammalian orthologs of invertebrate components of structures involved in mechanosensation (92) are the transduction channel in cutaneous sensory neurons, although acid-sensitive ion channels (ASICs) appear to play a role (11). Some progress has been made in the identification of proteins (e.g., stomatin-like protein 3 ref. 94) involved in sensing innocuous touch, but their genetic deletion in mouse does not compromise behavioral responses to noxious pressure. TRP channels are candidates based on expression and functional similarities to evolutionary counterparts, but whether these contribute to the molecular sensor/transducer or function in a sensitizing role is still unclear (11) (Table ​ (Table3). 3 ). The challenges encountered in assigning a role for transducers of noxious mechanical stimuli include the efficacy of stimulation protocols applied in behavioral and ex vivo tissue assays (e.g., phenotypes can differ when challenged with thin calibrated von Frey nylon filaments vs. distributed pinch that may also induce local ischemia ref. 95), the suppressive influence of innocuous A-fiber mechanosensitive inputs at a systems level (18), and the extrapolation of cellular assays to nociception (e.g., poking, ref. 96 stretching, ref. 97 hypo-osmotic–induced swelling, ref. 98). This topic is reviewed in more detail elsewhere (12, 19, 91�).


Content: Forward Biasing Vs Reverse Biasing

Basis for Comparison Forward Biasing Reverse Biasing
DefinitionThe external voltage which is applied across the PN-diode for reducing the potential barrier to constitutes the easy flow of current through it is called forward bias.The external voltage which is applied to the PN junction for strengthening the potential barrier and prevents the flow of current through it is called reverse bias.
Symbol
Connection The positive terminal of the battery is connected to the P-type semiconductor of the device and the negative terminal is connected to N-type semiconductor The negative terminal of the battery is connected to the P-region and the positive terminal of the battery is connected to N-type semiconductor.
Barrier Potential Reduces Strengthen
Voltage The voltage of an anode is greater than cathode.The voltage of cathode is greater than an anode.
Forward Current Large Small
Depletion layer Thin Thick
Resistance Low High
Current Flow Allows Prevents
Magnitude of Current Depends on forward voltage. Zero
Operate Conductor Insulator

Definition of Forward Biasing

In forward biasing the external voltage is applied across the PN-junction diode. This voltage cancels the potential barrier and provides the low resistance path to the flow of current. The forward bias means the positive region is connected to the p-terminal of the supply and the negative region is connected to the n-type of the device.

The potential barrier voltage is very small (nearly 0.7 V for silicon and 0.3 V for germanium junction) hence very few amount of voltage is required for the complete elimination of the barrier. The complete elimination of the barrier constitutes the low resistance path for the flow of current. Thus, the current starts flowing through the junction. This current is called forward current.

Definition of Reverse Biasing

In reversed bias the negative region is connected to the positive terminal of the battery and the positive region is connected to the negative terminal. The reverse potential increases the strength of the potential barrier. The potential barrier resists the flow of charge carrier across the junction. It creates a high resistive path in which no current flows through the circuit.



EXPERIMENT DESIGN SETUP WITH CLEAR LABELS

  1. Put on safety goggles, lab coats, gloves and masks for safety.
  2. Handle all materials carefully.
  3. Have a clear and clear working space for the experiment.
  4. Do not consume any of the materials used, and keep them away from the eyes.
  5. Complete all trials in the same area/room, at the same time of the day, using the same materials.
  6. Clean up the lab area after the experiment.
  7. Wash all materials thoroughly with warm water and soap after the experiment.

Laboratory Methods

Laboratory Methods Highlights

· This week, instead of stimulating a nerve with a reflex hammer via stretch receptors, we will stimulate a nerve directly with stimulating electrodes.

· Please wear short sleeves or sleeves that can be rolled above the elbow, half way up the brachium.

· A stimulating electrode delivers a mild electric shock, which, if sufficiently strong, depolarizes the membranes of neurons, causing them to fire.

· Neurons stimulated with stimulating electrodes behave like other neurons, except that when stimulating the fibers of a nerve, we may provoke action potentials in both sensory and motor fibers at the same time.

· In this lab we will stimulate the ulnar nerve and determine the outcome of increasing stimulus strength (in mAmps).

· Later, we will re-stimulate the ulnar nerve from two different locations along the arm in order to determine the conduction velocity.

Equipment Required: IXTA data acquisition unit, iWire-B3G cable and three EMG lead wires, disposable snap electrodes, HV stimulator lead wires.

I. Equipment Setup: Start the Software

Turn on the iWorx hardware box at the switch on the back, and select the Week7_NerveConduction.iwxset file from the P-drive.

II. Equipment Setup: Electrode Placement

  1. The subject should remove all jewelry from his/her left or right hand and wrist.
  2. Study the pathway of the ulnar nerve in the picture (below).

3. Clean the areas where the electrodes will be attached with an alcohol pad. Lightly abrade the skin in those areas.

  1. Obtain Seven disposable electrodes. Label 5 them on the pointed tab with the letters A through E.
  2. Cut down the electrodes so just the Medline logo shows. Keep the plastic backing on them to reduce adhesive build up on the scissors.
  • Place A on the medial edge of the little finger of the right hand, so the electrode button/snap is just above the first knuckle. This is for the RED (+) recording electrode in Figure HN-3-S2.
  • Place B on the medial edge of the palm, so the electrode button/snap is at the base of the little finger. This is for the BLACK (-) recording electrode on the hand.
  • Place C so the electrode button/snap is on the medialedge of the wrist just above the crease of the wrist. This is for the GREEN ground electrode on the hand.
  • Warning: Before connecting the IXTA stimulating electrodes to the subject, check the Stimulator Control Panel in the LabScribe toolbar to make sure the amplitude value is set to zero (0 AMP).

Next, attach the remaining 2 electrodes to the subject&rsquos arm so that they are placed on the pathway of the Ulnar Nerve in the following configuration:

  • Place D the medial edge of the forearm, so the electrode button/snap is above the wrist crease. Attach the BLACK (-) stimulating electrode.
  • Place E, the positive stimulating electrode, right above the negative stimulating electrode towards the medial side of the forearm. Attach the RED(+) stimulating electrode.
  • Electrodes F and G (in the photo) will be placed later for Exercise 2.
  • Videos of proper electrode placement for Exercises 1 and 2 are found on the P-Drive.

Safety precautions for this lab:

You will deliver mild electric shocks to either yourself or a volunteer experimental subject. The equipment you use to do this is carefully designed to keep the parameters of the electroshocks well within a safe range, and this experiment is safe and fun. Nevertheless, we ask that you place stimulating electrodes on the arms only, and only place electrodes on the same side of the body (never on both arms at the same time).

If you think you may be pregnant or if you suffer from known heart conditions or have an artificial heart pacemaker please do not volunteer as an experimental subject this week.


Why does a higher post-synaptic cell resistance lead to a higher voltage change when current is applied? - Psychology

Neural control initiates the formation of actin – myosin cross-bridges, leading to the sarcomere shortening involved in muscle contraction. These contractions extend from the muscle fiber through connective tissue to pull on bones, causing skeletal movement. The pull exerted by a muscle is called tension. The amount of force created by this tension can vary, which enables the same muscles to move very light objects and very heavy objects. In individual muscle fibers, the amount of tension produced depends primarily on the amount of cross-bridges formed, which is influenced by the cross-sectional area of the muscle fiber and the frequency of neural stimulation.

Muscle tension: Muscle tension is produced when the maximum amount of cross-bridges are formed, either within a muscle with a large diameter or when the maximum number of muscle fibers are stimulated. Muscle tone is residual muscle tension that resists passive stretching during the resting phase.

Cross-bridges and Tension

The number of cross-bridges formed between actin and myosin determine the amount of tension that a muscle fiber can produce. Cross-bridges can only form where thick and thin filaments overlap, allowing myosin to bind to actin. If more cross-bridges are formed, more myosin will pull on actin and more tension will be produced.

Maximal tension occurs when thick and thin filaments overlap to the greatest degree within a sarcomere. If a sarcomere at rest is stretched past an ideal resting length, thick and thin filaments do not overlap to the greatest degree so fewer cross-bridges can form. This results in fewer myosin heads pulling on actin and less muscle tension. As a sarcomere shortens, the zone of overlap reduces as the thin filaments reach the H zone, which is composed of myosin tails. Because myosin heads form cross-bridges, actin will not bind to myosin in this zone, reducing the tension produced by the myofiber. If the sarcomere is shortened even more, thin filaments begin to overlap with each other, reducing cross-bridge formation even further, and producing even less tension. Conversely, if the sarcomere is stretched to the point at which thick and thin filaments do not overlap at all, no cross-bridges are formed and no tension is produced. This amount of stretching does not usually occur because accessory proteins, internal sensory nerves, and connective tissue oppose extreme stretching.

The primary variable determining force production is the number of myofibers (long muscle cells) within the muscle that receive an action potential from the neuron that controls that fiber. When using the biceps to pick up a pencil, for example, the motor cortex of the brain only signals a few neurons of the biceps so only a few myofibers respond. In vertebrates, each myofiber responds fully if stimulated. On the other hand, when picking up a piano, the motor cortex signals all of the neurons in the biceps so that every myofiber participates. This is close to the maximum force the muscle can produce. As mentioned above, increasing the frequency of action potentials (the number of signals per second) can increase the force a bit more because the tropomyosin is flooded with calcium.


Voltage determines the kind of chemistry at each electrode. Gold is purified by plating the anode to the cathode at minimum voltage for the half-reaction, so impurities either do not dissolve and do not plate out. Copper electrorefining electrode mud contains valuable trace elements in concentrated from.

Current determines the amount of chemistry,

96,500 coulombs/mole of electrons.

Cell internal resistance converts input energy, power multipleid by time, $ce$, into useless heat. You then want small electrode spacing and good electrolyte stirring. You then need enough voltage to do the chemistry, plus more to compensate for resistance losses, but not so much voltage that undesirable chemistries are enabled. Does cell resistance increase (ohmic) or decrease with temperature?

Regarding your question: "Is the resistance fixed, or can I do anything to lower it?"

The energy used in electrolysis produces both product and waste heat. Naturally, you want to maintain sufficient production while limiting wasted energy.

A few important formulas:

Things that effect resistance, and their effects on product versus waste heat and rate of production: Adjusting each parameter individually:

Voltage: Per unit of energy supplied, in general, a lower voltage produces more product and less waste heat from electrolysis. Below a certain threshold voltage no electrolysis will occur. Although less power is consumed to produce the same product at a low voltage at a higher efficiency, the process proceeds slower because with a lower voltage, there is less current and power is consumed more slowly. Alternativly one can increase the voltage to drive more current and produce their product faster, but this happens at an expence to efficency.

Electrolyte type and concentration: Different electrolytes have different capacities to conduct and Its concentration above or below an ideal will negatively effect the electrolyte's capactiy to conduct electricity.

Temperature: Increasing the temperature of electrolyte lowers the resistance of an electrolyte. Additionally, some of the energy used to break up water's molecular bonds is provided by the thermal energy of molecules bouncing off each other. But, the effect really only becomes appreciable with high temperature electrolysis, like say 800c.

Surface Area: Surface area and current are proportional. All other parameters being equale, if you double the surface area of your electrodes, you effectivly half the resistance and double the current.

Spacing: Decreasing the spacing between electrodes decreases resistance.


Content: Forward Biasing Vs Reverse Biasing

Basis for Comparison Forward Biasing Reverse Biasing
DefinitionThe external voltage which is applied across the PN-diode for reducing the potential barrier to constitutes the easy flow of current through it is called forward bias.The external voltage which is applied to the PN junction for strengthening the potential barrier and prevents the flow of current through it is called reverse bias.
Symbol
Connection The positive terminal of the battery is connected to the P-type semiconductor of the device and the negative terminal is connected to N-type semiconductor The negative terminal of the battery is connected to the P-region and the positive terminal of the battery is connected to N-type semiconductor.
Barrier Potential Reduces Strengthen
Voltage The voltage of an anode is greater than cathode.The voltage of cathode is greater than an anode.
Forward Current Large Small
Depletion layer Thin Thick
Resistance Low High
Current Flow Allows Prevents
Magnitude of Current Depends on forward voltage. Zero
Operate Conductor Insulator

Definition of Forward Biasing

In forward biasing the external voltage is applied across the PN-junction diode. This voltage cancels the potential barrier and provides the low resistance path to the flow of current. The forward bias means the positive region is connected to the p-terminal of the supply and the negative region is connected to the n-type of the device.

The potential barrier voltage is very small (nearly 0.7 V for silicon and 0.3 V for germanium junction) hence very few amount of voltage is required for the complete elimination of the barrier. The complete elimination of the barrier constitutes the low resistance path for the flow of current. Thus, the current starts flowing through the junction. This current is called forward current.

Definition of Reverse Biasing

In reversed bias the negative region is connected to the positive terminal of the battery and the positive region is connected to the negative terminal. The reverse potential increases the strength of the potential barrier. The potential barrier resists the flow of charge carrier across the junction. It creates a high resistive path in which no current flows through the circuit.



The battery capacity specification (eg X mAh) tells you that your battery can run for 1 hour providing X milliamps until it is depleted. This doesn't always scale with time, for example you probably won't run for 1/2 hour if you draw 2*X milliamps, but this is another discussion.

To answer your question, a greater mAh will allow you to use your battery for longer before it depletes, in terms of current draw.

However, for the same battery model, the C-rating ($C$)(the maximum current you can safely, constantly draw from the battery) stays constant. Thus, since it is defined as $I_ = C cdot X$, higher C-ratings will also allow you to draw higher instantaneous currents, hence more power.

Neither, it means more energy and it implies more power.

Think of energy as the thing you "spend" to do work, and power is how much work you get done in a particular period of time.

Typically a battery is rated for power with something called a "C" rating, or how much power it would take to drain the battery in one hour.

Since output power of a battery is voltage times current, the C rating can be calculated as nominal voltage times the amp-hour rating, divided by the nominal voltage times an hour.

The nominal voltage cancels itself, and you're just left with the "amp" portion of the battery's amp-hour rating.

This means a 5000mAh battery has a 1C rating of 5000mA, but the output power of the battery is that times nominal voltage, so a 5000mAh battery pack rated for 1C would have less power available than a 2500mAh pack rated for 10C because the 5Ah pack's available output power is limited to (voltage) times 5A where the 2.5Ah pack's available output power is limited to (voltage) times 25A. The smaller pack, with the higher C rating, is capable of delivering 5 times the power in this example.

Regarding run times, that depends on the C rating for the battery. The higher it is, the more power you are (safely) able to draw at once, which means that you can get more power from a high C battery but, because power is how quickly you're spending energy, that means you'll drain the battery faster.

Ultimately, though, assuming the batteries have the same C rating, the larger capacity battery will have more power available because the C rating is driven by battery capacity.

Given the same applied load (meaning you don't actually use all that available power), the battery with the larger capacity will last longer because you are now drawing power at a lower C value.

I understand C values can be confusing, so if you want some examples just let me know!

I have mentioned several times now the phrase "available power" because of what I worry is a misconception about batteries and electricity in general. Just because a battery can deliver 25A doesn't mean the battery will deliver 25A. The cold cranking amperage rating (CCA) on your car battery is in the hundreds of amps, but if all you're doing is listening to the radio with your car off, you're drawing a negligible amount of power.

This is all because of Ohm's Law, which says that the current through a device is equal to the applied voltage, relative to the resistance in that device. That is, $I = frac$ (more commonly expressed as $V=IR$).

This means that if you don't change the electrical load - you keep the same motors running at the same speed - then the effective resistance of the load doesn't change. This in turn means that, if you don't change the terminal voltage of the battery, the current supplied to the load doesn't change.

If the voltage is constant, and the current is constant, then the applied power is constant, even if the available power changes. When your phone is in your hand, the battery inside the phone is powering it. When you plug your phone in, you might be connecting it electrically to a turbine the size of a strip mall. The change in available power doesn't mean you automatically consume all of the available power.

By this, I mean that, as long as your current battery is capable of supplying the load (your voltage bus doesn't brown out), then switching to a larger capacity battery will not improve your performance at all, even though it may have more available power. Electrical devices "take what they need" and nothing more.


3 Answers 3

The answer depends on the circumstances: how do you change the resistance? Both the drift velocity and the number of available charge carriers can be changed.

In a basic Drude model for electrical transport both, $n$, the charge carrier density and $ au$, the time between collisions determine the resistance:

$mathbf = left( frac ight) mathbf.$ Here, $mathbf$ is the current density and $mathbf$ the applied electrical field. The term in parentheses characterizes the material properties, i.e. its resistance.

By changing to a different material you can influence both, $n$ and $ au$, so both cases are possible.

Your understanding is correct. From $V=IR$ if voltage stays the same while resistance is increased, the current should be decreased.

But if you have heard of another equation $I = frac$

If current(I) is increased and the charge $Q$ is fixed (Charge is fixed if the power supply is from power cells like battery). Time will be decreased.

Which means that

The charges are moving faster! Because numbers of charge are fixed by the size of battery.

Imagine a four lanes road. Then in 300 meters ahead, there is a construction for road maintenance for three lanes. Making only one lane available to pass. Cars from 4 lanes must combine into one lane, making traffic jams and cause everyone to get home slower.

4 lanes road = Normal wire

1 lane road and traffic jams = Problems cause by resistance.

Home= + terminal of battery

Like some phone battery have 10000mAh. Which actually is the value of $Q$ but in milliamperes * hours not ampere * seconds. So 1 mAh is equal to 5/18 Coulomb.


Transduction of noxious mechanical stimuli

Whereas heat- and chemical-induced nociceptor responses correlate with pain perception in humans (9, 24), mechanical stimulation of C-MH (24) and rapidly adapting A-HTM (18) fibers may not (24) (Tables ​ (Tables1 1 and ​ and2). 2 ). The perception of pinprick pain intensity, however, is related to activity in capsaicin-insensitive A-fiber nociceptors (e.g., A-M and A-MH type I) (78). Transduction channels mediating mammalian noxious (and innocuous) mechanical stimuli have been elusive (5, 91, 92). Transduction in soma membranes on a submillisecond time scale suggests direct gating by pressure of ion channels with NSC and possibly Na + permeability (91). No orthologs for the well-studied prokaryotic mechanosensitive channels MscL and MscS are present in mammalian genomes (93). In addition, there is no strong evidence that mammalian orthologs of invertebrate components of structures involved in mechanosensation (92) are the transduction channel in cutaneous sensory neurons, although acid-sensitive ion channels (ASICs) appear to play a role (11). Some progress has been made in the identification of proteins (e.g., stomatin-like protein 3 ref. 94) involved in sensing innocuous touch, but their genetic deletion in mouse does not compromise behavioral responses to noxious pressure. TRP channels are candidates based on expression and functional similarities to evolutionary counterparts, but whether these contribute to the molecular sensor/transducer or function in a sensitizing role is still unclear (11) (Table ​ (Table3). 3 ). The challenges encountered in assigning a role for transducers of noxious mechanical stimuli include the efficacy of stimulation protocols applied in behavioral and ex vivo tissue assays (e.g., phenotypes can differ when challenged with thin calibrated von Frey nylon filaments vs. distributed pinch that may also induce local ischemia ref. 95), the suppressive influence of innocuous A-fiber mechanosensitive inputs at a systems level (18), and the extrapolation of cellular assays to nociception (e.g., poking, ref. 96 stretching, ref. 97 hypo-osmotic–induced swelling, ref. 98). This topic is reviewed in more detail elsewhere (12, 19, 91�).


Memristor-Based Neural Networks

Neuron Biological Mechanisms and Memristive Synapse

The human brain can solve complex tasks, such as image recognition and data classification, more efficiently than traditional computers. The reason why a brain excels in complicated functions is the large number of neurons and synapses that process information in parallel. As shown in Figure 3, when an electrical signal is transmitted between two neurons via axon and synapse, the joint strength or weight is adjusted by the synapse. There are approximately 100 billion neurons in an entire human brain, each with about 10,000 synapses. Pre-synaptic and post-synaptic neurons transfer and receive the signal of excitatory and inhibitory post-synaptic potentials by updating synaptic weights. Long-term potentiation (LTP) and long-term depression (LTD) are important mechanisms in a biological nervous system, which indicates a deep-rooted transformation in the connection strengths between neurons. According to the interval between pre-synaptic and post-synaptic action potentials or spikes, the phenomenon of synaptic weight modification is known as spike-timing-dependent plasticity (STDP) (Yan et al., 2018a, 2019c). Due to scalability, low power operation, non-volatile features, and small on-chip area, memristors are good candidates for artificial synaptic devices to mimicking the LTP, LTD, and STDP behaviors (Jo et al., 2010 Ohno et al., 2011 Kim et al., 2015 Wang et al., 2017 Yan et al., 2017).

Figure 3. Schematic of two interconnected neurons by synapses.

There are some key requirements for memristive devices in neural network applications. For example, a wide range of resistance is required to enable sufficient resistance states devices are required to have low resistance fluctuations and low device-to-device variability a higher absolute resistance is required for low power dissipation and high durability is required for reprogramming and training (Choi et al., 2018 Yan et al., 2018b, 2019a Xia and Yang, 2019). A concern with device stability is resistance drift, which occurs over time or with the environment. Resistance drift causes undesirable changes in synapse weight and blurs different resistance states, ultimately affecting the accuracy of neural network computation (Xia and Yang, 2019). To deal with this drift challenge, improvements can be made in three aspects: (1) material device engineering, (2) circuit design, and (3) system design (Alibart et al., 2012 Choi et al., 2018 Jiang et al., 2018 Lastras-Montaño and Cheng, 2018 Yan et al., 2018b, 2019a Zhao et al., 2020). For example, as for the domain of material engineering, threading dislocations can be used to control programming variation and enhance switching uniformity (Choi et al., 2018). In terms of circuit-level design, a module of two series memristors and a transistor with the smallest size can be used, thus, the resistance ratio of the memristor can be encoded to compensate for the resistance drift (Lastras-Montaño and Cheng, 2018). For the system-design level, device deviation can be reduced by protocols, such as closed loop peripheral circuit with a write-verify function (Alibart et al., 2012). In order to obtain linear and symmetric weight update in LTP and LTD for efficient neural network training, optimized programming pulses can be used to excite memristors with either fixed-amplitude or fixed-width voltage pulses (Jiang et al., 2018 Zhao et al., 2020). Note it is inevitable to increase energy consumption if the memristor resistance value is changed through complex programmable pulses.

The comparison of different memristive synapse circuit structures is shown in Table 2 (Kim et al., 2011a Wang et al., 2014 Prezioso et al., 2015 Hong et al., 2019 Krestinskaya et al., 2019). Single memristor synapse (1M) crossbar arrays in neural networks have the lowest complexity and low power dissipation. However, it suffers from sneak path problems and complex peripheral switch circuits. Synapses with two memristors (2M) have a more flexible weight range and better symmetric LTP and LTD, but the corresponding chip area will be doubled. A synapse with one memristor and one transistor (1M-1T) has the advantage of solving the sneak path problem, but it also occupies a large area in the large-scale integration of neural networks. A bridge synapse architecture with four memristors (4M) provides a bidirectional programming mechanism with a voltage input voltage output. Due to the significant on-chip area overhead, the 1M-1T and 4M synapses may not be applicable for large-scale neural networks.

Table 2. Comparison of different structure memristive synapse circuit.

Memristor-Based ANNs

The basic operations of classical hardware ANNs include multiplication, addition, and activation, which are accomplished by CMOS circuits such as GPUs. The weights are typically saved in SRAM or DRAM. Despite the scalability of CMOS circuits, they are still not enough for ANN applications. Furthermore, the SRAM cell size are too big to be integrated at high density. DRAM needs to be refreshed periodically to prevent data decay. Whether it is SRAM or DRAM, it often needs to interact with CMOS cores. No matter SRAM or DRAM, the data needs to be fetched by to the cache and register files of the digital processors before processing and returned through the same databus, leading to significant speed limit and large energy consumption, which is the main challenge for deep learning and big data applications (Xia and Yang, 2019). Nowadays, ANNs feature for large number of computational parameters stored in memory compared to classical computation. For example, a two-layer 784-800-10 fully-connected deep neural network in the MNIST dataset has 635,200 interconnections. A state of the art keep neural network like Visual Geometry Group (VGG) has a few millions of parameters. These factors pose a huge challenge to the implementation of ANN hardware. The memristor's non-volatility, lower power consumption, lower parasitic capacitance, and reconfigureable resistance states, high speed, and adaptability lead to a key role in ANN applications (Xia and Yang, 2019). An ANN is an information processing model which are derived from mathematical optimization. A typical ANN architecture and its memristor crossbar are shown in Figure 4. The system usually consists of three layers: an input layer, a middle layer or a hidden layer, and an output layer. The connected units or nodes are neurons which are usually series by weighted-sum module and activation function module. Neurons also perform tasks of decoding, control, and signal routing. Due to its powerful signal processing capability, CMOS analog and digital logic circuits are the best candidates for neurons hardware implementation. In Figure 4, arrow or connecting lines represent synapses, and their weights represent the connection strengths between two neurons. Assume the weight modulation matrix Wij in a memristor synapse crossbar is a M × N dimensinal matrix, where i(i = 1, 2, …, N) and j(i = 1, 2, …, M) are the index numbers of the output and input ports of the memristor crossbar. Wij between pre-neuron input vector Xj and post-neuron output vector Yi is a matrix-vector multiplication operation, expressed as Equation (1) (Jeong and Shi, 2018).

The matrix W can be continuously adjusted until the difference between the output value y and the target value y * is minimized. The Equation (2) shows the synaptic weight tunning process with the gradient of output error (y–y * ) 2 under a training rate (Huang et al., 2018). Therefore, a memristor crossbar is equal to a CMOS adder plus a CMOS multiplier and an SRAM (Jeong and Shi, 2018), because data are computed, stored, and regenerated on the same local device (i.e., a memristor itself). Besides, a crossbar can be vertically integrated into three dimensions (Seok et al., 2014 Lin et al., 2020 Luo et al., 2020). In this way, it saves much chip area and power consumption. Due to the memristor synapse update and save weight data on itself, the memory wall problem with von Neumann bottleneck is solved.

Figure 4. Typical ANN architecture and its memristor crossbar.

Researchers have developed various topologies and learning algorithms for software-based or hardware-based ANNs. Table 3 provides a comparison of typical memristive ANNs, including single-layer perceptron (SLP) or multi-layer perceptron (MLP), CNN, cellular neural network (CeNN), and recurrent neural network (RNN). SLP and MLP are classic neural networks with well-known learning rules such as Hebbian learning, backpropagation. Although a lot of ANN studies have been verified by simulations or small-scale implementation, a single-layer neural network with 128 × 64 1M-1T Ta/HfO2 memristor array has been experimentally demonstrated with an image recognition accuracy of 89.9% for the MNIST dataset (Hu et al., 2018). CNNs (referred to as space-invariant or shift-invariant ANNs) are regularized versions of MLP. Their hidden layers usually contain multiple complex activation functions, and perform convolution or regional maximum value operations. Researchers have demonstrated an over 70% of accuracy in human behavior video recognition with a memristor-based 3D CNN (Liu et al., 2020). It should be emphasized that this verification is only a software simulation result, while the on-chip hardware demonstration is still very challenging, especially for deep CNNs (Wang et al., 2019a Luo et al., 2020 Yao et al., 2020). CeNN is a massively parallel computing neural network, whose communication features are limited to between adjacent cell neurons. The cells are dissipative non-linear continuous-time or discrete-time processing units. Due to their dynamic processing capability and flexibility, CeNNs are promising candidates for real-time high frame rate processing or multi-target motion detection. For example, a CeNN with 4M memristive bridge circuit synapse has been proposed for image processing (Duan et al., 2014). Unlike classic feed forward ANNs, RNNs have a feedback connection that enables temporal dynamic behavior. Therefore, it is suitable for speech recognition applications. Long short-term memory (LSTM) is a kind of useful RNN structure for deep learning. Hardware implementation of LSTM networks based on memristors have been reported (Smagulova et al., 2018 Li et al., 2019 Tsai et al., 2019 Wang et al., 2019a).

Table 3. Typical architectures of Memristive ANNs.

Due to atomic-level random defects and variability in the conductance modulation process, non-ideal memristor characteristics are the main causes of learning accuracy loss in ANNs. This phenomenon is manifested in the following aspects of memristor: asymmetric non-linear weight change between potentiation and depression, limited ON/OFF weight ratio and device variation. Table 4 shows the main strategies for how to deal with these issues. One can mitigate the effects of non-ideal memristor characteristics on ANN accuracy from four levels: device materials, circuits, architectures, and algorithms. At device materials level, switching uniformity and analog on/off ratio can be enhanced by optimizing redox reaction at the metal/oxide interface, adopting threading dislocations technology or heating element (Jeong et al., 2015 Lee et al., 2015 Tanikawa et al., 2018). At circuits level, one can use customized excitation pulse or hybrid CMOS-memristor synapses to mitigate memristor non-ideal effects (Park et al., 2013 Li et al., 2016 Chang et al., 2017 Li S. J. et al., 2018 Woo and Yu, 2018). At architectures level, common techniques are multiple memristors cell for high redundancy, pseudo-crossbar array, and peripheral circuit compensation (Chen et al., 2015). Co-optimization between memristors and ANN algorithms is also reported (Li et al., 2016). However, it should be noted that implementation of these strategies inevitably brings side effects, such as high manufacturing cost, large power consumption, large chip area, complex peripheral circuits, or inefficient algorithm. For example, the non-identical pulse excitation or bipolar-pulse-training methods improve the linearity and symmetry of memristor synapses, but it increases the complexity of peripheral circuits, system power consumption, and chip area. Therefore, trade-offs and co-optimization need to be made at each design level to improve the learning accuracy of ANNs (Gi et al., 2018 Fu et al., 2019). Figure 5 is a collaborative design example from bottom-level memristor devices to top-level training algorithms (Fu et al., 2019). The conductance response (CR) curve of memristors is first measured to obtain its non-linearity factor. Then, the CR curve is divided into piecewise linear segments to obtain their slope, and the pulse width of the excitation pulse is inversely proportional to the slope. These data are stored in memory for comparison and correction by memristor crossbars during the update. Through this method, the ANN recognition accuracy is finally improved.

Table 4. ANNs learning accuracy improvement by mitigating memristor non-ideal effects.

Figure 5. Co-design from memristor non-ideal characteristics to the ANN algorithm (Fu et al., 2019).

The memristor-based ANN applications can be software, hardware or hybrid (Kozhevnikov and Krasilich, 2016). Software networks tend to be more accurate than their hardware counterparts because they do not have the analog element non-uniformity issues. However, hardware networks feature better speed and less power consumption due to non-von Neumann architectures (Kozhevnikov and Krasilich, 2016). In Figure 6, a deep neuromorphic accelerator ANN chip with 2.4 million Al2O3/TiO2-xmemristors was designed and fabricated (Kataeva et al., 2019). This memristor chip consists of a 24 × 43 array with a 48 × 48 memristor crossbar at each intersection, which means its complexity is about 1,000 times higher than previous designs in the literature. This work is a good starting point for the operation of medium-scale memristor ANNs. Similar accelerators have appeared in the last 2 years (Cai et al., 2019 Chen W.-H. et al., 2019 Xue et al., 2020).

Figure 6. A deep neuromorphic ANN chip with 2.4 million memristor devices (Kataeva et al., 2019).

Memristive neural networks can be used to understand human emotion and simulate human operational abilities (Bishop, 1995). The well-known PavlTov associative memory experiment has been implemented in memristive ANNs with a novel weighted-input-feedback learning method (Ma et al., 2018). As more input signals, neurons, and memristor synapses, complex emotional processing will be achieved in further AI chips. Due to the material challenge and the lack of effective models, most of the demonstrations are limited to small-scale simulations for simple tasks. The shortcomings of memristors are mainly the non-linearity, asymmetry, and variability, which seriously affect the accuracy of ANNs. Moreover, the peripheral circuits and interface must provide superior energy efficiency and data throughput.

Memristor-Based SNN

Inspired by cognitive and computational methods of animal brains, the third-generation neural network, SNN, makes desirable properties of compact biological neurons mimic and remarkable cognitive performance. The most prominent feature of SNN is that it incorporates the concept of time into operations with discrete values, while the input and output values of the second-generation ANNs are continuous. SNN can better leverage the strength of biological paradigm of information processing, thanks to the hardware emulation of synapses and neurons. ANN is calculated layer by layer, which is relatively simple. However, spike trains in SNN are relatively difficult to understand and efficient coding methods for these spike trains are not easy. These dynamic events driven spikes in SNN enhance the ability to process spatio-temporal or real-world sensory data, with fast adaptation and exponential memorization. The combination of spatio-temporal data allows SNN to process signals naturally and efficiently.

Neuron models, learning rules, and external stimulus coding are key research areas of SNN. The Hodgkin & Huxley (HH) model, leaky Integrate-and-Fire (LIF) model, spike response model (SRM), and Izhikevich model are the most common models of neurons (Hodgkin and Huxley, 1952 Chua, 2013 Ahmed et al., 2014 Pfeiffer and Pfeil, 2018 Wang and Yan, 2019 Zhao et al., 2019 Ojiugwo et al., 2020). The HH model is a continuous-time mathematical model based on conductance. Although this model is based on the study of squid, it is widely used in lower or higher organisms (even humans being). However, since complex non-linear differential equations are set with four variables, this model is difficult to achieve high accuracy. Chua established the memristor model of Hodgkin-Huxley neurons and proved that memristors can be applied to the imitation of complex neurobiology (Chua, 2013). The Izhikevich model integrates the bio-plasticity of HH model with simplicity and higher computational efficiency. The HH and Izhikevich models are calculated by differential equations, while the LIF and SRM models are computed by an integral method. SRM is an extended version of LIF, and the Izhikevich model can be considered as a simplified version of the Hodgkin-Huxley model. These mathematical models are the results of different degrees of customization, trade-offs and biological neural network optimization. Table 5 shows a comparison of several memristor-based SNNs. It can be seen that these SNN studies are based on STDP learning rules and LIF neurons. Most of them are still in simple pattern recognition applications, only a few of which have hardware implementations.

Table 5. Comparison of several memristor-based SNNs.

The salient features of SNNs are as follows. First, biological neuron models (e.g., HH, LIF) are closer to biological neurons than neurons of ANN. Second, the transmitted information is time or frequency encoded discrete-time spikes, which can contain more information than traditional networks. Third, each neuron can work alone and enter a low power standby mode when there is no input signal. Since SNNs have been proven to be more powerful than ANNs in theory, it is natural to widely use SNNs. Since the spike training cannot be differentiated, the gradient descent method cannot be used to train SNNs without losing accurate temporal information. Another problem is that it takes a lot of computation to simulate SNNs on normal hardware, because it requires analog differential equations (Ojiugwo et al., 2020). Due to the complexity of SNNs, efficient learning rules that meet the characteristics of biological neural networks have not been discovered. This rule is required to model not only synaptic connectivity but also its growth and attenuation. Another challenge is the discontinuous nature of spike sequence, which makes many classic ANN learning rules unsuitable for SNNs, or can only be approximated, because the convergence problem is very serious. Meanwhile, many SNNs studies are limited to theoretical analysis and simulation of simple tasks rather than complex and intelligent tasks (e.g., multiple regression analysis, deductive and inductive reasoning, and their chip implementation) (Wang and Yan, 2019). Although the future of SNNs is still unclear, many researchers believe that SNNs will replace deep ANNs. The reason is that AI is essentially a biological brain mimicking process, and SNNs can provide a perfect mechanism for unsupervised learning.

As shown in Figure 7, a neural network is implemented with CMOS neurons, CMOS control circuits, and memristor synapses (Sun, 2015). The aggregation module, leaky integrate and fire module are equivalent to the role of dendrites and axon hillocks, respectively. Input neurons signals are temporally and spatially summed through a common-drain aggregation amplifier circuit. A memristor synapse gives the action potential signal a weight and its output signal, that is, a post-synaptic potential signal is transmitted to post-neurons. Using the action potential signal and feedback signals from post-neurons, the control circuit and synaptic update phase provide potentiation or depression signals to memristor synapses. According to the STDP learning rules, the transistor-level weight adjustment circuit is composed of a memristor device and CMOS transmission gates. The transmission gates are controlled by potentiation or depression signals. The system is very similar to the main features of biological neurons, which is useful for neuromorphic SNN hardware implementation. A more complete description of SNN circuits and system applications is shown in Figure 8 (Wu and Saxena, 2018). The system consists of event-driven CMOS neurons, a competitive neural coding algorithm [i.e., winner take all (WTA) learning rule], and multi-bit memristor synapse array. A stochastic non-linear STDP learning rule with an exponential shaped window learning function is adopted to update memristor synapse weights in situ. The amplitude and additional temporal delay of the half rectangular half-triangular spike waveform can be adjusted for dendritic-inspired processing. This work demonstrates the feasibility and excellence of emerging memristor devices in neuromorphic applications, with low power consumption and compact on-chip area.

Figure 7. CMOS neuron and memristor synapse weight update circuit (Sun, 2015).


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